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ARA2000
Address-Programmable Reverse Amplifier with Step Attenuator
FEATURES
* * * * * * * * * * * * * Low cost integrated amplifier with step attenuator Attenuation Range: 0-58 dB, adjustable in 1dB increments via a 3 wire serial control Meets DOCSIS distortion requirements at a +60dBmV output signal level Programmable address allows multiple parts to share control bus Low distortion and low noise Frequency range: 5-100MHz 5 Volt operation -40 to +85 oC temperature range MCNS/DOCSIS Compliant Cable Modems CATV Interactive Set-Top Box Telephony over Cable Systems OpenCable Set-Top Box Residential Gateway circuit design that exceeds the MCNS/DOCSIS requirement for harmonic performance at a +60dBmV output level while only requiring a single polarity +5V supply. Both the input and output are matched to 75 ohms with an appropriate transformer. The precision attenuator provides up to 58 dB of attenuation in 1 dB increments. The ARA2000 has a programmable address that allows multiple devices to share a common control bus. The ARA2000 is offered in a 28-pin SSOP package featuring a heat slug on the bottom of the package.
Data Sheet - Rev 2.2
APPLICATIONS S12 Package 28 Pin SSOP with Heat Slug
PRODUCT DESCRIPTION
The ARA2000 is designed to provide the reverse path amplification and output level control functions in a CATV Set-Top Box or Cable Modem. It incorporates a digitally controlled precision step attenuator that is preceded by an ultra low noise amplifier stage, and followed by an ultra-linear output driver amplifier. This device uses a balanced
Clock Data Enable
Balun
ARA2000
Low Pass Filter
Transmit Enable/Disable
Upstream QPSK/16QAM Modulator
Clock Data
RAM
ROM
5-42 MHz
2
Address Control
MAC
Clock Data
Microcontroller with Ethernet MAC
44 MHz
Diplexer
54-860 MHz
DoubleConversion Tuner
SAW Filter
QAM Receiver with FEC
10Base-T Transceiver
RJ45 Connector
Figure 1: Cable Modem or Set Top Box Application Diagram
06/2004
ARA2000
GaAs IC
ATTIN (+) A1OUT (+) A1IN (+)
32 dB 16 dB 8 dB 4 dB 2 dB 1 dB
ATTOUT (+) A2IN (+) A2OUT (+) ISET2
EFET
ISET1 Vg1 A1IN (-) A1OUT (-) ATTIN (-)
EFET
Vg2 A2OUT (-) A2IN (-) ATTOUT (-)
32 dB P5
16 dB P4
8 dB P3
4 dB P2
2 dB P1
1 dB P0
Buffer
Clock
Buffer
2
Data
2-Bit Shift Register/ Address
8
Control Latch
Data Latch
Enable
8
2 8
2-Bit Shift Register / Die ID
4-Bit Shift Register / Chip Select
8-Bit Shift Register
Die Address 0
CMOS IC (Serial to Parallel Interface)
Die Address 1
Figure 2: Functional Block Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14
GND VATTN ATTIN (+) A1OUT (+) A1IN (+) Vg1 ISET1 A1IN (-) A1OUT (-) ATTIN (-) VCMOS CLK DAT EN
GND N/C ATTOUT (+) A2IN (+) A2OUT (+) Vg2 ISET2 A2OUT (-) A2IN (-) ATTOUT (-) GNDCMOS N/C C1 C0
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Figure 3: Pin Out 2
Data Sheet - Rev 2.2 06/2004
ARA2000
Table 1: Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NAME GND VATTN ATTIN (+) A1OUT (+) A1IN (+) V g1 ISET1 A1IN (-) A1OUT (-) ATTIN (-) VCMOS C LK DAT EN DESCRIPTION Ground Supply for Attenuator Attenuator (+) Input (2) Amplifier A1 (+) Output Amplifier A1 (+) Input (2) Amplifier A1 (+/-) Control Amplifier A1 (+/-) Current Adjust Amplifier A1 (-) Input (2) Amplifier A1 (-) Output Attenuator (-) Input (2) Supply For Digital CMOS Circuit Clock Data Enable PIN 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME C0 C1 N/C GNDCMOS ATTOUT (-) A2IN (-) A2OUT (-) ISET2 V g2 A2
OUT
DESCRIPTION Device Address 0 Device Address 1 No Connection (1) Ground for Digital CMOS Circuit Attenuator (-) Output (2) Amplifier A2 (-) Input (2) Amplifier A2 (-) Output Amplifier A2 (+/-) Current Adjust Amplifier A2 (+/-) Control Amplifier A2 (+) Output Amplifier A2 (+) Input (2) Attenuator (+) Output (2) No Connection (1) Ground
(+)
A2 IN (+) ATTOUT (+) N/C GND
Notes: (1) All N/C pins should be grounded. (2) Pins should be AC-coupled. No external DC bias should be applied.
Data Sheet - Rev 2.2 06/2004
3
ARA2000
ELECTRICAL CHARACTERISTICS
Table 2: Absolute Minimum and Maximum Ratings
PARAMETER Analog Supply (pins 2, 4, 9, 21, 24) Digital Supply: VCMOS (pin 11) Amplifier Controls Vg1, Vg2 (pins 6, 23)
RF Power at Inputs (pins 5, 8)
MIN 0 0 -5 -0.5 -55 -
MAX 9 6 2 +60 VCMOS+0.5 +200 260 5
UNIT VD C VD C V dBmV V
0
Digital Interface (pins 12, 13, 14, 15, 16) Storage Temperature Soldering Temperature Soldering Time
C C
0
S ec
Stresses in excess of the absolute ratings may cause permanent damage. Functional operation is not implied under these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability. Notes: 1. Pins 3, 5, 8, 10, 19, 20, 25 and 26 should be AC-coupled. No external DC bias should be applied. 2. Pins 7 and 22 should be grounded or pulled to ground through a resistor. No external DC bias should be applied.
Table 3: Operating Ranges
PARAMETER Amplifier Supply: VDD (pins 4, 9, 21, 24) Attenuator Supply: VATTN (pin 2) Digital Supply: VCMOS (pin 11) Digital Interface (pins 12, 13, 14, 15, 16) Amplifier Controls Vg1, Vg2 (pins 6, 23) Case Temperature
MIN 4.5 VDD-0.5 3.0 0 -5 -40
TYP 5 5 1 25
MAX 7 7 5.5 VCMOS 2 85
UNIT VD C VD C VD C V V
0
C
The device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications.
4
Data Sheet - Rev 2.2 06/2004
ARA2000 Table 4: DC Electrical Specifications TA=25C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (TX enabled); Vg1, Vg2 = 0 V (TX disabled)
PARAMETER Amplifier A1 Current (pins 4, 9) Amplifier A2 Current (pins 21, 24) Attenuator Current (pin 2) Total Power Consumption
MIN -
TYP 48 2.4 77 3.7 9 0.67 75
MAX 80 6 120 9 15 1.08 150
UNIT mA mA mA W mW
COMMENTS Tx enabled Tx disabled Tx enabled Tx disabled
Tx enabled Tx disabled
Table 5: AC Electrical Specifications TA=25C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (TX enabled); Vg1, Vg2 = 0 V (TX disabled)
PARAMETER Gain (10 MHz) Gain Flatness Gain Variation over Temperature Attenuation Steps 1 dB 2 dB 4 dB 8 dB 16 dB 32 dB MIN 27.5 0.65 1.6 3.6 7.5 15.0 30.2 58.6 78 TYP 29.3 0.75 1.5 -0.006 0.83 1.70 3.75 7.75 15.40 30.75 60.3 -75 -60 68.5 3.0 MAX 30.5 1.00 2.05 4.0 8.0 15.8 31.3 -53 -53 4.0 UNIT dB dB dB/C COMMENTS 0 dB attenuation setting 5 to 42 MHz 5 to 65 MHz
dB
Monotonic
Maximum Attenuation 2nd Harmonic Distortion Level (10 MHz) 3rd Harmonic Distortion Level (10 MHz) 3rd Order Output Intercept 1 dB Gain Compression Point Noise Figure
Note: As measured in ANADIGICS test fixture
dB dB c dB c dBmV dBmV dB Includes input balun loss +60 dBmV into 75 Ohms +60 dBmV into 75 Ohms
Data Sheet - Rev 2.2 06/2004
5
ARA2000
continued: AC Electrical Specifications TA=25C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (TX enabled); Vg1, Vg2 = 0 V (TX disabled)
PARAMETER Output Noise Power Active / No Signal / Min. Atten. Set. Active / No Signal / Max. Atten. Set. Isolation (45 MHz) in Tx disable mode
MIN
TYP
MAX
UNIT
COMMENTS
-
65
-38.5 -53.8 -
dBmV
Any 160 kHz bandwidth from 5 to 42 MHz Difference in output signal between Tx enable and Tx disable between pins 5 and 8 (Tx enabled) with transformer (Tx enabled) Tx enabled Tx disabled between pins 21 and 24 with transformer Tx enabled Tx disabled 0 dB attenuator setting 24 dB attenuator setting
dB
Differential Input Impedance Input Impedance Input Return Loss (75 Ohm characteristic impedance) Differential Output Impedance Output Impedance Output Return Loss (75 Ohm characteristic impedance) Output Voltage Transient Tx enable / Tx disable
Note: As measured in ANADIGICS test fixture
-
300 75 -20 -5 300 75 -17 -15 4
-12 -12 -10 100 7
Ohms Ohms dB Ohms Ohms dB mVp-p
6
Data Sheet - Rev 2.2 06/2004
Control A1 0 / +3 V +5 V +5 V
Control A2 0 / +3 V
1uF 2K Ohms 1uF 1K Ohms 0.1uF
27
2K Ohms 1K Ohms 0.1uF
1
2K Ohms 470pF VATTN ATTIN (+) 470pF 470pF A1OUT (+) A1IN (+) Vg1 ISET1 A1IN (-) A1OUT (-) ATTIN (-) VCMOS CLK DAT EN ARA2000 GNDCMOS 18 N/C 17 C1 16 C0 15 A2IN (-) 20 ATTOUT (-) 19 A2OUT (-) 21 Vg2 23 ISET2 22 A2OUT (+)
24 2
10uH N/C ATTOUT (+) 26 A2IN (+) 25 2K Ohms
3
GND
GND
28
RF Input (75 Ohms) 1000pF
4 5 6 7
1000pF
Turns Ratio 1:2 1.2K Ohms
Turns Ratio 2:1
1500pF
RF Output (75 Ohms)
3.9 Ohms
8 9
1.2K Ohms 1000pF
10
Toko Balun 616PT-1030 470pF
Clock
Data
Enable
Figure 4: Test Circuit
1000pF
11 12
Data Sheet - Rev 2.2 06/2004
10uH 1uF
13 14
1uF
Note: Tx Enable: Control A1 and Control A2 = +3V Tx Disable: Control A1 and Control A2 = 0V
0.1uF
0.1uF
+5 V
+5 V
Note: Pins 15 and 16 are grounded on the ANADIGICS test fixture, identifying device address "00".
ARA2000
7
ARA2000
PERFORMANCE DATA
Figure 5: Attenuation Level vs Control Word
64 60 56 52 48 44 40 36 32 28 24 20 16 12 8 4 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 Control Word
Attenuation (dB)
Figure 6: Gain & Noise Figure vs Frequency
Gain 35 30 25 Gain (dB) 20 15 10 5 10 30 50 Frequency (MHz) 70 90 Noise Figure 8 7 6 5 4 3 2 NF (dB)
6 5 3 2 Measured @ 30 MHz 20 3 4 5 VDD ( Volts ) 6 7 1 NF (dB) 4
Figure 7: Gain & Noise Figure vs VDD
35 Gain Noise Figure
32 GAIN (dB)
29
26
23
8
Data Sheet - Rev 2.2 06/2004
ARA2000
Figure 8: Gain & Noise Figure vs Temperature
35 Gain Noise Figure 6
32 GAIN (dB)
5
26
3
23 Measured @ 30 MHz 20 -40 -25 -10 5 20 35
o
2
1 50 65 80
Temperature (C )
Figure 9: Harmonic Distortion vs VDD
POUT = 58dBmV
2nd Harmonic -20 -30 Harmonic Level (dBc) -40 -50 -60 -70 Measured @ 5 MHz -80 3 4 5 VDD ( Volts ) 6 7 3rd Harmonic
Figure 10: Harmonic Distortion vs VDD
POUT = 58dBmV
2nd Harmonic -20 -30 Harmonic Level (dBc) -40 -50 -60 -70 Measured @ 12 MHz -80 3 4 5 VDD ( Volts ) 6 7 3rd Harmonic
Data Sheet - Rev 2.2 06/2004
NF (dB)
29
4
9
ARA2000 Figure 11: Harmonic Distortion vs Temperature
POUT = 58dBmV
2nd Harmonic -40 -45 Harmonic level (dBc) -50 -55 -60 -65 -70 -75 -80 -40 -25 -10 5 20 35
o
3rd Harmonic
Measured @ 5 MHz 50 65 80
Temperature (C )
Figure 12: Harmonic Distortion vs Power Out
2nd -30 -35 -40 Harmonics (dBc) -45 -50 -55 -60 -65 -70 -75
49 51 53 55 57 59 61 63 65 67
3rd
Pout (dBmV)
Figure 13: Transients vs Attenuation
POUT = 55dBmV at 0dB attenuation
DOCSIS 1.1 Spec. 100 90 80 Transient (mV) 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 Power Attenuation (dB)
ARA2000 ARA2001
10
Data Sheet - Rev 2.2 06/2004
ARA2000 Figure 14: Harmonic Performance over Frequency POUT = +62dBmV
2nd Harmonic -50 -52 Harmonic Level (dBc) -54 -56 -58 -60 -62 -64 -66 -68 -70 -72 0 5 10 15 20 Frequency (MHz) 25 30 35 40 3rd Harmonic
Figure 15: IIP2 & IIP3 vs Frequency
IIP2 40 IIP3 14
36 IIP2 (dBm)
12 IIP3 (dBm)
IIP3 (dBm)
32
10
28
8
24
Measured @ V DD = 5 Volts Pin = -20 dBm per tone 5 15 25 35 45 55 65 75 85 95
6
20 Frequency (MHz)
4
Figure 16: IIP2 & IIP3 vs VDD
IIP2 40 IIP3 15
36
11
IIP2 (dBm)
32
7
28
3
24 Measured @ 65 MHz Two tones @ 29.5 MHz 20 3 4 5 VDD (Volts) 6 7
-1
-5
Data Sheet - Rev 2.2 06/2004
11
ARA2000
LOGIC PROGRAMMING
Programming Instructions The programming word is set through a 16 bit shift register via the data, clock and enable lines. The data is entered in order with the most significant bit (MSB) first and the least significant bit (LSB) last.
The enable line must be low for the duration of the data entry, then set high to latch the shift register. The rising edge of the clock pulse shifts each data value into the register.
Table 6: Programming Word
DATA BIT Value D 15 P7 D 14 P6 D 13 P5 D 12 P4 D11 P3 D 10 P2 D9 P1 D8 P0 D7 0 D6 0 D5 0 D4 1 D3 C1 D2 C0 D1 1 D0 1
Table 7: Data Description
VALUE P7 P6 P5 P4 P3 P2 P1 P0 FUNCTION (1 = on, 0 = bypass) N/A N/A 32 dB Attenuator Bit
1 C1 0
Table 8: Device Address
LOGIC LEVEL INPUT TO ADDRESS DEVICE C0 0 0 1 1 Pin 16 (C1) 0 1 0 1 Pin 15 (C0) 0 0 1 1
16 dB Attenuator Bit 8 dB Attenuator Bit 4 dB Attenuator Bit 2 dB Attenuator Bit 1 dB Attenuator Bit
0 1
The device is selected when the logic inputs at pins 16 and 15 match the values of data bits C1 and C0, respectively.
DATA
D15: MSB
D14
D8
D7
D1
D0: LSB
CLOCK
ENABLE OR ENABLE
Figure 17: Serial Data Input Timing 12
Data Sheet - Rev 2.2 06/2004
ARA2000
APPLICATION INFORMATION
Transmit Enable / Disable The ARA2000 includes two amplification stages that each can be shut down through external control pins Vg1 and Vg2 (pins 6 and 23, respectively.) By applying a slightly positive bias of typically +1.0 Volts, the amplifier is enabled. In order to disable the amplifier, the control pin needs to be pulled to ground. A practical way to implement the necessary control is to use bias resistor networks similar to those shown in the test circuit schematic (Figure 4.) Each network includes a resistor shunted to ground that serves as a pull-down to disable the amplifier when no control voltage is applied. When a positive voltage is applied, the network acts as a voltage divider that presents the required +1.0 Volts to enable the amplifier. By selecting different resistor values for the voltage divider, the network can accommodate different control voltage inputs. The Vg1 and Vg2 pins may be connected together directly, and controlled through a single resistor network from a common control voltage. Amplifier Bias Current The ISET pins (7 and 22) set the bias current for the amplification stages. Grounding these pins results in the maximum possible current. By placing a resistor from the pin to ground, the current can be reduced. The recommended bias conditions use the configuration shown in the test circuit schematic in Figure 4.
Thermal Layout Considerations The device package for the ARA2000 features a heat slug on the bottom of the package body. Use of the heat slug is an integral part of the device design. Soldering this slug to the ground plane of the PC board will ensure the lowest possible thermal resistance for the device, and will result in the longest MTF (mean time to failure.) A PC board layout that optimizes the benefits of the heat slug is shown in Figure 18. The via holes located under the body of the device must be plated through to a ground plane layer of metal, in order to provide a sufficient heat sink. The recommended solder mask outline is shown in Figure 19.
Figure 18: PC Board Layout
Data Sheet - Rev 2.2 06/2004
13
ARA2000 Output Transformer Matching the output of the ARA2000 to a 75 Ohm load is accomplished using a 2:1 turns ratio transformer. In addition to providing an impedance transformation, this transformer provides the bias to the output amplifier stage via the center tap. The transformer also cancels even mode distortion products and common mode signals, such as the voltage transients that occur while enabling and disabling the amplifiers. As a result, care must be taken when selecting the transformer to be used at the output. It must be capable of handling the RF and DC power requirements without saturating the core, and it must have adequate isolation and good phase and amplitude balance. It also must operate over the desired frequency and temperature range for the intended application.
ESD Sensitivity Electrostatic discharges can cause permanent damage to this device. Electrostatic charges accumulate on test equipment and the human body, and can discharge without detection. Proper precautions and handling are strongly recommended. Refer to the ANADIGICS application note on ESD precautions.
Figure 19: Solder Mask Outline
14
Data Sheet - Rev 2.2 06/2004
ARA2000
PACKAGE OUTLINE
Figure 20: S12 Package Outline - 28 Pin SSOP with Heat Slug
Data Sheet - Rev 2.2 06/2004
15
ARA2000
COMPONENT PACKAGING
Volume quantities of the ARA2000 are supplied on tape and reel. Each reel holds 3,500 pieces.
Figure 21: Reel Dimensions
DIRECTION OF FEED
Figure 22: Tape Dimensions 16
Data Sheet - Rev 2.2 06/2004
ARA2000
NOTES
Data Sheet - Rev 2.2 06/2004
17
ARA2000
NOTES
18
Data Sheet - Rev 2.2 06/2004
ARA2000
NOTES
Data Sheet - Rev 2.2 06/2004
19
ARA2000
ORDERING INFORMATION
ORDER NUMBER ARA2000S12P1 TEMPERATURE RANGE -40 to 85 C PACKAGE DESCRIPTION 28 Pin SSOP with Heat Slug COMPONENT PACKAGING 3,500 piece tape and reel
ANADIGICS, Inc.
141 Mount Bethel Road Warren, New Jersey 07059, U.S.A. Tel: +1 (908) 668-5000 Fax: +1 (908) 668-5132 URL: http://www.anadigics.com E-mail: Mktg@anadigics.com IMPORTANT NOTICE
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change prior to a product's formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders.
WARNING
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product in any such application without written consent is prohibited.
20
Data Sheet - Rev 2.2 06/2004

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